The majority of present day integrated circuits are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through an underlying channel between the source and drain regions.
The conductivity of the channel region, upon formation of the conductive channel due to the application of an appropriate control voltage to the gate electrode, depends upon, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as the channel length of the transistor. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, since the speed of creating the channel, which depends in part on the conductivity of the gate electrode, and the channel resistivity substantially determine the characteristics of the transistor, the scaling of the channel length, and associated therewith the reduction of channel resistivity, are dominant design efforts used to increase the operating speed of the integrated circuits.
For many early integrated circuit device technology generations, the gate electrode structures of most transistor elements have included a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polycrystalline silicon (“polysilicon”) gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller in order to increase the operating speed, many newer generation devices employ gate electrode stacks including alternative materials in an effort to avoid the short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of from about 14 to about 32 nm, gate electrode stacks including a so-called high-k dielectric/metal gate (HK/MG) configuration have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations. One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique.
Even with the use of replacement metal gate technologies, conventional contact structures that are used to connect to the source and drain regions of the transistors began to limit device performance in several ways. First, it was not possible to minimize the contact resistance, if the contact hole was also of minimum size, and problems with cleaning the small contact holes became a concern. In addition, the area of the source/drain regions could not be minimized because the contact hole had to be aligned to these regions with a separate masking step, and extra area had to be allocated for misalignment, which resulted in increased source/drain-to-substrate junction capacitance and decreased the speed of the device. When non-minimum-width MOSFETs were manufactured with conventional contacts, several small, uniform sized contact holes were usually used rather than one wider contact hole. The problem with using several small, equally sized contact holes rather than one wider one, was that the full width of the source/drain region was thus not available for the contact structure. As a result, the device contact resistance was proportionally larger than it would have been in a device having minimum width.
A proposed method of solving the problem associated with shrinking the MOSFET involves selective growth of silicon and diffusion of the implanted dopants to form the junctions. In this approach, silicon is selectively grown (SSG) over the source/drain regions of the MOSFET to a depth of, for example, about 200 to about 400 nm, following the completion of oxide-spacer formation. The SSG step produces what is known in the art as “raised” source/drain regions, which assist in alleviating the aforementioned contact size problems in smaller-scale devices.
The use of raised source/drain structures in connection with high-k/metal gate process flows, however, has given rise to further operational problems. For example, the conductive contact plugs that are used for electrical connection to the source/drain regions create an undesirable capacitor (two conductors separated by a dielectric material) between the metal gate electrode and the conductive contact plugs. This undesirable “fringe” capacitor must be charged and discharged every switching cycle of the transistor. Such problems may result in a circuit exhibiting longer rise/fall times for a given switching cycle, and hence slower operating speeds.
Accordingly, with the increasing use of raised source/drain structures in high-k/metal gate process flows, it is desirable to provide techniques and structures that avoid the undesirable fringe capacitance that has been experienced in prior art techniques and structures. Additionally, it is desirable to provide methods for the fabrication of such structures that are easily integrated into existing process flow schemes used in semiconductor fabrication facilities. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.